1. Field of the Invention
The present invention relates to a logic circuit optimizing method and arts related thereto for generating circuit information supplied to a logic emulation device that verifies logic of a semiconductor integrated circuit.
2. Description of the Related Art
Large scaled LSIs (large scale integrated circuits) in recent years have made it impossible to verify a logic circuit by a software simulation.
Therefore, a logic emulation device that reproduces (emulates) circuit operation by hardware is used.
The logic emulation device is roughly classified into two types.
One is a processor-type logic emulation device that emulates with great calculating ability with a plurality of processors installed in the device.
The other is an FPGA-type logic emulation device to emulate logic operation with a plurality of programmable devices (variable logic elements). The FPGA-type logic emulation device includes such as an FPGA (Field Programmable Gate Array) that allows users to change circuit operation freely.
Published Japanese Patent Application Laid-Open No. 2000-36737 (patent reference no. 1) disclosed an example of the FPGA-type emulation device as a prior art.
As is shown in FIG. 19, a logic emulation device 100 in the prior art is comprised of logic chips 101–103, a memory module 104, a user specification chip 105 and an interconnection chip 106.
Each of the logic chips 101–103 is an FPGA. The memory module 104 emulates a memory device. The user specification chip 105 is a hardware IP (intellectual property) such as an LSI used arbitrarily by users.
The interconnection chip 106 connects the logic chips 101–103, the memory module 104 and the user specification chip 105 mutually with crossbar switch structure.
The fundamental technique in allotting circuits to an FPGA, disclosed in the patent reference no. 1, will be described in the following.
A logic circuit is basically comprised of flip-flops and combining circuits that connect with these flip-flops.
Accordingly, a logic circuit is allotted to an FPGA in a unit of cluster. A cluster is a circuit group that is comprised of a combining circuit that exists from an input terminal of a flip-flop in the current stage toward an output terminal of a flip-flop or plural flip-flops in the previous stage. The extraction of a cluster is called clustering.
The clustering will be explained with the accompanying drawings.
FIG. 20 is a descriptive illustration of clustering. FIG. 20(a) is a schematic diagram of a logic circuit before clustering, and FIG. 20(b) is a schematic diagram of the logic circuit after clustering.
FIG. 20(a) illustrates an example of circuit structure that connects a flip-flop FF0 to flip-flops FF1 and FF2. The flip-flop FF0 and the flip-flops FF1 and FF2 are connected by a combining circuit.
In the example of the circuit structure of FIG. 20(a), when the clustering is practiced, a cluster 107 and a cluster 108 are made as shown in FIG. 20(b). The cluster 107 is comprised of a combining circuit 109 and the flip-flop FF1. The cluster 108 is comprised of a combining circuit 110 and the flip-flop FF2.
Such clustering will be practiced to all the flip-flops in the given circuit. The cluster created in this way will be allotted to an FPGA.
FIG. 21 is an exemplified illustration of clusters allotted to the FPGA. Clusters 111 are allotted to an FPGA 112 after clustering as shown in FIG. 21.
The technique of allotting a logic circuit to an FPGA in a unit of cluster has a purpose to avoid a lack in a number of I/O (input/output) of the FPGA, which is indicated by Rent's rule.
Rent's rule is a rule that shows the relationships between I/O pins (including block pins) and circuit scale in logic design, which was proposed by E. F. Rent of IBM in 1960. (http://www.cedcc.psu.edu/ee497 i/rents_rule.PDF).
The following expression is an equation given by Rent's rule.Np=Kp·Ngx  [Equation 1]
In Equation 1, “Np” is the number of I/O pins, and “Ng” is a circuit scale (the number of circuits (gates)). “X” is the Rent's constant, and “Kp” is a proportionality constant.
According to Rent's rule, the number of I/O pins increases in an exponential relationship with the circuit scale.
Process with thinner lines of today's semiconductors has made LSIs even more larger-scaled, which has made it more difficult to allot logic circuits to FPGAs.
Meanwhile, high-speed operation of the LSIs is also required; therefore, the number of the circuit stages among flip-flops tends to be the same or reduced. However, a degree of parallel of combining circuits has been increased.
This causes a problem that logic circuits are not allotted appropriately to FPGAs even after clustering.
For example, when a cluster to be allotted to an FPGA is larger than the remaining circuit scale available in the FPGA, the cluster will not be allotted to the FPGA, and will be allotted to another FPGA instead.
In this case, the utilization efficiency of the FPGA will be lowered, which causes a problem that the circuit scale that can be treated with a logic emulation device becomes smaller.
If the utilization efficiency of the FPGA is low, the circuit density to be allotted becomes smaller, and signal delay in the circuits becomes larger.
Accordingly, the signal delay is adversely added to the FPGA operation, which causes a problem that the operation speed or the emulation speed reduces.